The present invention relates to a semiconductor device, and more particularly to a semiconductor device which enables a down bonding and a mounting of a multi-pin in :semiconductor package.
The lead-on-chip (LOC) technique is introduced so as to make a large chip to be easily loaded in the standard package, for the semiconductor element, especially for a RAM-structured memory chip. And the strengthening of the chip characteristic was possible owing to the LOC technique.
Additionally, in a semiconductor memory device, method of down bonding the Vss or Vcc terminal is used for suppressing a latch-up so as to keep the characteristics of an element against the change of the external voltage for dynamic random access memory (DRAM). This method is also used for noise dispersion and speed enhancement for static random access memory (SRAM). The down bonding method means that the semiconductor element is connected with the pattern terminal for use in bonding formed on a top surface of the element, having the active surface of the element as a bottom surface thereof.
A bus-bar or conductive film is bonded in order to perform the down bonding in the LOC or chip-on-lead (COL) type semiconductor package wherein the chip attach pad is not provided. However, the mounting of multi-pin for this case is difficult.
The down bonding method of the conventional semiconductor package by referring to FIG. 1 to FIG. 6 is explained as follows:
First, FIGS. 1 and 2 acre the embodiments of the conventional bonding method, and illustrate the down bonding method for plastic package when the lead frame wherein the die attach pad is provided is used. FIG. 1 shows the case when the tie bar connected to die pad is down-bonded, while FIG. 2 shows the case when the wing-tip of die pad is down-bonded.
Referring to FIG. 1 and FIG. 2, when the sawing process wherein a multiple of chips formed on semiconductor wafer are sawed into separate chips and the quality chips are selected among the above separated chips is finished, the above quality chips 1 are detached from wafer. Then, the detached chips are attached on a die pad 8, and the wire bonding wherein bonding pads 2 and 3 of chip 1 are connected as shown in 5 and 5' to leads 4 and 4' is performed. At this time, the down bonding which supports a specific pad among the bonding pads of chip 1 is performed, and a tie bar 6 which supports die pad 8 is down-bonded 7 in FIG. 1, while a wing-tip 9, i.e., a protrusion of die pad 8 is down-bonded in FIG. 2.
FIG. 3 and FIG. 4 are the sectional views of FIG. 1 and FIG. 2, respectively.
As shown in FIG. 3 and FIG. 4, chip 1 separated from the semiconductor wafer is attached on die pad 8 whereon a conductive adhesive 10 is deposited. Then, a down bonding 7 is performed to tie bar 6 which supports die pad 8 or to wing-tip 9.
FIG. 5 and FIG. 6 show the embodiments of the bonding method of the conventional LOC type-package, and explain the down bonding method for the case of using the lead frame wherein the chip attach pad is not provided. FIG. 5 shows the case when the conductive film is used, while FIG. 6 shows the case when the bus-bar is used.
Referring to FIG. 5 and FIG. 6, the wire bonding which connects (15 and 15') a bonding pad 17 of the chip and leads 19 and 19' on each individual chip 11 separated from the semiconductor wafer is performed after the sawing process is completed. At this time, down bonding which supports the specific pad among the bonding pads of the chip is performed, and down bondings 12, 12', 13 and 14 are performed for a conductive film 16 on chip 11 in FIG. 5, while down bondings 12, 14, 15 and 15' are performed for Vcc or Vss bus-bars 20 and 21 in FIG. 6. The reference numerals 16', 17' and 18 which are not explained in FIGS. 5 and 6 indicate an insulating tape, a bus-bar bonding pad and a Vcc or Vss lead, respectively.
Size of the conductive film and bus-bar region cannot be sufficiently expanded, when the down bonding is performed for the above conventional LOC-type package, and accordingly, the mounting of multi-pin is difficult.